An ASIC Design Solution Supporting Mission-Critical Applications
Reliable MicroSystems provides ASIC integrated circuit design of specialized custom-design as a turn-key delivery of custom-design IP or prototype silicon die, or through the targeted engineering support at any phase of the customer’s product maturation.
Experienced ASIC Circuit Design Engineers
Reliable MicroSystems engineers are experienced ASIC circuit designers with proven success in executing digital, analog, and mixed-signal circuit design from conception through silicon fabrication at all of the major foundries and the most advanced technology nodes.
First-Pass Success Nodes
At Reliable MicroSystems, we have demonstrated first-pass success at the 180nm, 130nm, 90nm, 45nm, 40nm, 32nm, 28nm, 20nm, and 14nm technology nodes. Our team is extensively knowledgeable of the complexities of modern PDK, foundry flow, and vertically-integrated EDA design infrastructure.
The critical bridge between a design concept and confidently proceeding with physical implementation is the deployment of modeling and simulation to verify desired functionality.
Design To Deployment
The critical bridge between a design concept and confidently proceeding with physical implementation is the deployment of modeling and simulation to verify desired functionality. Mission-critical systems operating in harsh operating environments, e.g. space, require the capability to assess the impact of the environment on the function and reliability of the system. Historically, this has been accomplished through a design, fabricate, test, and redesign cycle, where the testing focused on the response of the circuit to environmental stimuli. However, this process has both a high financial and schedule impact that hampers the characterization and design of mission-critical components within the 12 to 18-month new technology node introduction cycle. Modeling and simulation advancements have reduced this design-test-redesign cycle in state-of-the-art commercial electronics design, where electrical reliability and performance over process, voltage, and temperature variation are critical.
Incorporation Of Models
The incorporation of other environmental models into the commercial EDA flows for integrated circuit design would allow prediction, during the design cycle, of environment driven responses and failures prior to actual circuit fabrication. The Rel-Micro engineering team has decades of experience in developing methods to study and simulate the impact of radiation on integrated circuit devices used in mission-critical applications. The fundamental challenge, from a scientific perspective, is that radiation-matter interactions are very physical, localized events – often occurring on the nanometer scale; and IC circuit design occurs at a much higher level of abstraction – often at the level of pre-designed standard circuit cells that are automatically placed on an integrated circuit floorplan and wired together to perform the desired function.
While powerful tools exist to analyze radiation effects at the microscopic level, such tools are impractical at the EDA level due to the sheer scale of computational power required for simulation of just a few transistors. These tools are excellent for the study of radiation mechanisms and the elucidation of potential vulnerabilities at the transistor levels, but are impractical for integrated circuit design. On the other hand, modern simulations admirably reproduce circuit operation at the compact model level (e.g. SPICE) and higher levels (behavioral, Boolean), but do not capture the physical subtleties of a radiation interaction at nano-scale transistor geometries.
A Unique Approach
The Rel-Micro approach is unique. We are developing a “bottom-up” scientific approach; building on a legacy of scientific discovery and radiation modeling to “push” this information up the design hierarchy to enable predictive radiation-hardening-by-design (RHBD) analysis at the EDA level. This vertically-integrated, radiation-aware design (VIRAD) methodology is being integrated with industry standard design toll flows. VIRAD includes analysis capabilities to identify vulnerabilities at the schematic and topological levels to inform RHBD mitigation efforts prior to physical implementation. VIRAD also includes layout-aware analysis capabilities to inform device placement and critical-node spacing variants for identical schematic designs during circuit layout, as shown in the figures below.
Technology surprise does not materialize in a vacuum – it accompanies the absolute cutting-edge of technology advancements and the relentless exploitation of Moore’s Law scaling toward faster, better, more capable systems.
Technology Surprise – High-Impact But Unexpected Developments As Technology Progresses – Can Cut Both Ways.
Technology breakthroughs can enable new applications or rapid progression of existing capabilities. However, unintended consequences of technology maturation often occur. The relentless pursuit of faster, better, more capable systems on the cutting edge of science and engineering can introduce surprises – not all of them desirable.
One important microelectronic technology surprise that has accompanied Moore’s Law scaling of integrated circuits has been the increasing susceptibility of integrated circuits to soft faults – including externally-generated errors from natural or manmade radiation or internally-generated errors from stochastic processes – with each scaled technology generation.
While extrinsic errors and faults can be inconvenient in commercial microelectronics, they can be devastating in mission-critical or “must not fail” systems. As a result, such high-reliability microelectronics have historically “lagged” the state-of-the-art in terms of sophistication or technology generation. Often it is expedient to pursue what one knows, rather than venturing into uncharted territory. Legacy technology has often been the safest option in cases of high-regret potential failure.
Actionable Knowledge Is The Key To Overcoming These Limitations.
A program for the insertion of the most advanced commercial technologies into mission-critical applications is enabled by designer access to sophisticated models and simulations, comprehensive technology information, and appropriate test devices for the characterization of extreme environmental conditions (for example, radiation, temperature, or stress) that may take the system outside of the nominal design specifications.
Rel-Micro engineers have developed portable test chip structures for reliability characterization of the most advanced technology nodes (custom test coupons). These test coupons include basic test structures (technology characterization vehicles or TCVs) and novel test circuits (circuit test vehicles or CTVs) for characterization of the resiliency of advanced technologies in hostile environments.
Rel-Micro staff have developed simulation and modeling tools that allow designers to predict the response of technologies to radiation effects prior to fabrication and testing. Failures can be discovered, and mitigation techniques developed, before the first part is built or deployed.
Once the vulnerabilities of a technology are known, Rel-Micro engineers are accomplished in the development and application of novel radiation-hardened design techniques (RHBD) for the mitigation of failure in a technology for specific customer applications. Whether space-bound, military mission-critical, or commercial “cannot fail” deployment, Rel-Micro-designed circuits can fulfill customer-supplied specifications and metrics through system-level, circuit-level, and technology-level solutions.
Reliable MicroSystems Engineers Have Operational Experience In The Following Areas:
- The assessment of the performance of advanced technologies via characterization through custom test coupons
- The modeling and simulation of radiation-induced faults and failures to predict vulnerabilities of technologies and designs, and assess risk in mission-critical deployment
- The development of test methods and plans for predicting the performance and survival of electronics in radiation environments
- The development and validation of radiation hardened by design mitigation techniques in advanced semiconductor technologies to enable the engineering of resilient designs
- The implementation of microelectronic designs in all current pure-play integrated circuit foundry technology nodes